It is the end of September 2026. In Year 3 of the computer science and telecommunications track at an Italian technical high school, the subject Sistemi e reti (systems and networks, 4 hours a week) has opened the year with the Von Neumann architecture and is now moving on to the machine cycle — fetch, decode, execute. After that come memory, then assembly on a teaching machine or on Arduino. The first test falls in five to seven weeks, so between the end of October and the start of November: a written theory paper plus questions on a block diagram.
You can learn the block diagram of the CPU in one afternoon. The problem comes when the teacher asks you to trace what happens inside those blocks while the machine executes an instruction, register by register. That is exactly the kind of question that appears most often in a test.
The Von Neumann model in brief
According to Von Neumann, a computer is made of four components connected by buses:
- CPU (Central Processing Unit), itself divided into the ALU (Arithmetic Logic Unit, which does the calculations) and the CU (Control Unit, which coordinates the machine cycle), plus a set of registers;
- main memory, a single memory that holds both the data and the instructions of the program — this is the distinctive feature of the model: data and instructions share the same memory space and the same bus;
- I/O units, which connect the computer to keyboard, screen, disk and network;
- system bus: three separate channels — the data bus (carries the values), the address bus (carries the memory location to read or write) and the control bus (carries the signals that coordinate the operation, such as read/write).
The alternative model often quoted for comparison is the Harvard architecture, used in many microcontrollers. Data memory and instruction memory are physically separate, with separate buses, and this lets simple CPUs read an instruction and a piece of data in the same clock cycle. Von Neumann is simpler to build (one memory, one bus) but it pays a price: the CPU and the memory compete for the same channel to read both the code and the data. This is the so-called Von Neumann bottleneck. In a test it is enough to state this difference in three lines: nothing more is needed.
The registers the machine cycle really uses
You can only understand the machine cycle once the registers involved are clear. They are few, and each one has a precise job:
- PC (Program Counter): holds the address of the next instruction to execute. It increments automatically after every fetch.
- IR (Instruction Register): holds the instruction just fetched from memory, waiting to be decoded.
- MAR (Memory Address Register): holds the address the CPU is about to send to memory, whether to read or to write.
- MDR (Memory Data Register, sometimes called MBR, Memory Buffer Register): holds the data passing between CPU and memory at that moment — on a read it comes from memory, on a write it is ready to be written.
- Accumulator (ACC): the register where the ALU puts the result of arithmetic or logic operations, on teaching machines with a single accumulator.
- Flags (or status register): a small set of bits that signal conditions on the result of the last operation — for example zero (Z, the result is 0) or carry (C, there was a carry). They are used for conditional jumps.
The machine cycle, step by step
Every instruction, whatever it is, goes through three phases that repeat in a continuous loop as long as the machine is on:
- Fetch: the PC holds the address of the instruction to execute. That address is copied into the MAR, the CU sends the read signal on the control bus, memory returns the contents of that cell on the data bus, and those contents are copied into the IR. At this point the PC is incremented, so it already points to the next instruction.
- Decode: the CU reads the contents of the IR and works out which instruction it is (add, load, jump, …) and which operands it needs.
- Execute: the CU activates the right circuits — typically the ALU, if it is an arithmetic operation — and the result ends up where it has to go: in the accumulator, in a register, or back in memory through the MAR and MDR.
After execute the cycle starts again from fetch, with the PC already pointing to the next instruction. This endless repetition is why we talk about a “cycle”: it is not a sequence that ends, it is a loop that stops only when the program meets a halt instruction or the machine is switched off.
A mistake to avoid: confusing the address with the data
Watch out: the most frequent mistake on this topic is confusing what the MAR holds with what the MDR holds. The MAR always and only holds an address (a location); the MDR always and only holds a datum (a value). If you write in a test “the MAR contains the number 25” when 25 is the value to add, and not the memory cell where that value sits, you lose marks even if you have understood the rest of the cycle. One way to avoid it: before writing the trace of an instruction, note next to each register whether you expect an address or a value — MAR and PC are always addresses, MDR and ACC are always values, and the IR holds the instruction code.
A second common mistake is forgetting that the PC is incremented during the fetch, not during the execute. If in a jump (JUMP) the new address is written into the PC during the execute, that automatic increment from the fetch is simply overwritten — not added twice.
Three worked examples
Exercise 1 — tracing the machine cycle on three instructions.
A teaching machine with an accumulator runs this program, with data memory starting at cell 100:
0: LOAD 100 ; load into ACC the contents of cell 100
1: ADD 101 ; add to ACC the contents of cell 101
2: STORE 102 ; write ACC into cell 102With MEM[100] = 7 and MEM[101] = 5, the register-by-register trace is:
| Phase | PC | IR | MAR | MDR | ACC |
|---|---|---|---|---|---|
| fetch instr. 0 | 0→1 | LOAD 100 | 0 | LOAD 100 | — |
| decode+execute | 1 | LOAD 100 | 100 | 7 | 7 |
| fetch instr. 1 | 1→2 | ADD 101 | 1 | ADD 101 | 7 |
| decode+execute | 2 | ADD 101 | 101 | 5 | 12 |
| fetch instr. 2 | 2→3 | STORE 102 | 2 | STORE 102 | 12 |
| decode+execute | 3 | STORE 102 | 102 | 12 | 12 |
At the end, MEM[102] = 12. Note how the MAR alternates between the address of the instruction (during the fetch) and the address of the operand (during the execute): the same register serves both purposes, at different moments of the cycle.
Exercise 2 — address bus and memory capacity.
How many distinct memory cells can a 16-bit address bus express, and how much memory does it address if every cell holds a 1-byte word?
An -bit bus can represent different combinations, so distinct addresses:
With a 1-byte word per cell, the total addressable memory is:
If the same 16-bit bus addressed 4-byte (32-bit) words instead of 1-byte ones, the total memory would rise to bytes, that is 256 KiB. With the same address bus, the only thing that changes is how many bytes fit in each cell.
Exercise 3 — clock and duration of an instruction.
A CPU runs at 2 GHz and an instruction takes on average 4 clock cycles to complete fetch, decode and execute. How long does that instruction take to execute?
A 2 GHz clock means cycles per second, so the duration of one cycle is:
With 4 cycles per instruction:
That CPU therefore executes about 500 million instructions of this kind per second (). This is why a test asks you for both the number of cycles per instruction and the frequency: either one alone is not enough to answer “how long does it take”.
Memory: the hierarchy in three lines
The syllabus goes on to the memory hierarchy, and it helps to have the outline clear before you get there: registers (inside the CPU, a few bytes, top speed) → cache (small, very fast, a temporary copy of the most-used data) → RAM (main memory, volatile: it empties when the power goes off) → disk (mass storage, non-volatile, much slower but large). As you go down the hierarchy you gain capacity and lose speed. It is the same trade-off that governs almost every hardware design choice you will meet from here on.
For the base-2 calculations needed for buses and addresses — conversions, powers of two, hexadecimal — you will find the step-by-step method in binary and hexadecimal in Year 1 at the technical school: here I have taken it as known. If in the computer science subject itself you are already working on loops, arrays and functions, that part of the syllabus (different from Sistemi e reti) is covered in nested loops and arrays in Year 3 computer science. And when in Year 4 Sistemi e reti moves from hardware to networking, the next level — IP addresses and subnetting — is here: IP addresses and subnetting in Year 4 at the technical school.
Frequently asked questions
Is cache memory part of the CPU or of the RAM? It is physically close to the CPU (often built into the same chip) but conceptually it is an intermediate level: a fast, small copy of data that also sits in RAM, managed automatically by the hardware.
Why is the model called “Von Neumann” and not “the computer”? Because it is not the only possible model — there is also the Harvard architecture, with separate memories for data and instructions — and it is associated with John von Neumann, who in 1945 first described the idea of a program stored together with the data in the same memory.
Do I need to know all the register abbreviations by heart? You need to know how to use them in the trace of an instruction, as in exercise 1: the abbreviation alone, without being able to say what it contains at that precise step of the cycle, is worth little in a test.
If you want to see what the ALU I keep mentioning is made of, the answer lies in logic gates: I explained them in the post on logic gates and Karnaugh maps.
There is no computer science practice test on the site yet for this topic: the school practice tests we do have, for now maths and physics, are on the school practice tests page. For the rest of the computer science syllabus you will find material on the computer science page; if you want a hand with this topic, start with the free introductory call.
